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| the following document contains information on cypress products. the document has the series name, product name, and ordering part numbering with the prefix mb. however, cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix cy. how to check the ordering p art n umber 1. g o to www.cypress.com/pcn . 2. enter the keyword ( for example , ordering part number) i n the search pcns field and click apply . 3. click the corresponding title from the search results. 4. download the affected parts list file , which has details of all changes for more information please contact your local sales office for additional information about cypress products and solutions. about cypress cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. cypress' microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated products and get them to market first. cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. to learn more, go to www.cypress.com .
mb95560h series mb95570h series mb95580h series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04629 rev. *d revised september 27, 2017 the mb95560h/570h/580h is a series of general-purpose, single-chi p microcontrollers. in addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. features f 2 mc-8fx cpu core ? instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test bran ch instructions ? bit manipulation instructions, etc. clock (the main osci llation clock and the suboscillation clock are only available on mb95f562h/f562k/f563h/f563k/ f564h/f564k/f582h/f582k/f583h/f583k/f584h/f584k.) ? selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum ma- chine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz ? 2%) - the main cr clock frequency becomes 8 mhz when the pll multiplication rate is 2. - the main cr clock frequency becomes 10 mhz when the pll multiplication rate is 2.5. - the main cr clock frequency becomes 12 mhz when the pll multiplication rate is 3. - the main cr clock frequency becomes 16 mhz when the pll multiplication rate is 4. ? selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer ? 8/16-bit composite timer ? 2 channels (only one channel on mb95f572h/f572k/f573h/f573k/f574h/f574k/f582h/ f582k/f583h/f583k/f584h/f584k) ? time-base timer ? 1 channel ? watch prescaler ? 1 channel lin-uart (only available on mb95f562h/f562k/f563h/ f563k/f564h/f564k/f582h/f582k/f583h/f583k/f584h/ f584k) ? full duplex double buffer ? capable of clock synchronous serial data transfer and clock asynchronous serial data transfer external interrupt ? interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected. low power consumption (standby) modes ? there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode ? in standby mode, the device can be made to enter either normal standby mode or deep standby mode. i/o port ? mb95f562h/f563h/f564h (maximum no. of i/o ports: 16) - general-purpose i/o ports (cmos i/o): 15 - general-purpose i/o ports (n-ch open drain): 1 ? mb95f562k/f563k/f564k (maximum no. of i/o ports: 17) - general-purpose i/o ports (cmos i/o): 15 - general-purpose i/o ports (n-ch open drain): 2 ? mb95f572h/f573h/f574h (maximum no. of i/o ports: 4) - general-purpose i/o ports (cmos i/o): 3 - general-purpose i/o ports (n-ch open drain): 1 ? mb95f572k/f573k/f574k (maximum no. of i/o ports: 5) - general-purpose i/o ports (cmos i/o): 3 - general-purpose i/o ports (n-ch open drain): 2 ? mb95f582h/f583h/f584h (maximum no. of i/o ports: 12) - general-purpose i/o ports (cmos i/o): 11 - general-purpose i/o ports (n-ch open drain): 1 ? mb95f582k/f583k/f584k (maximum no. of i/o ports: 13) - general-purpose i/o ports (cmos i/o): 11 - general-purpose i/o ports (n-ch open drain): 2 on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer power-on reset ? a power-on reset is generated when the power is switched on. low-voltage detection reset circuit (only available on mb95f562k/f563k/f564k/f572k/f573k/f574k/f582k/ f583k/f584k) ? built-in low-voltage detector clock supervisor counter ? built-in clock supervisor counter function dual operation flash memory ? the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simul- taneously. flash memory security function ? protects the content of the flash memory. document number: 002-04629 rev. *d page 2 of 88 mb95560h series mb95570h series mb95580h series contents features............................................................................. 1 1. product line-up ............................................................ 3 2. packages and corresponding products.................... 7 3. differences among products and notes on product selection ............................................................. 8 4. pin assignment ............................................................ 9 5. pin functions (mb95560h series, 32 pins) .............. 11 6. pin functions (mb95560h series, 20 pins) .............. 13 7. pin functions (mb95570h series, 8 pins) ................ 15 8. pin functions (mb95580h series, 32 pins) .............. 16 9. pin functions (mb95580h series, 16 pins) .............. 18 10. i/o circuit type ......................................................... 20 11. handling precautions............................................... 21 11.1 precautions for product design......................... 21 11.2 precautions for package mounting ................... 23 11.3 precautions for use envi ronment...................... 24 12. notes on device handling....................................... 24 13. pin connection ......................................................... 25 14. block diagram (mb95560h series) ......................... 26 15. block diagram (mb95570h series) ......................... 27 16. block diagram (mb95580h series) ......................... 28 17. cpu core................................................................... 29 18. i/o map (mb95560h series) ..................................... 30 19. i/o map (mb95570h series) ..................................... 34 20. i/o map (mb95580h series) ..................................... 37 21. interrupt source table (mb 95560h series)............ 40 22. interrupt source table (mb 95570h series)............ 41 23. interrupt source table (mb 95580h series)............ 42 24. electrical characteristics... ...................................... 43 24.1 absolute maximum rating s............................... 43 24.2 recommended operating conditions ............... 45 24.3 dc characteristics ......... ................................... 46 24.4 ac characteristics.......... ................................... 49 24.5 a/d converter.................................................... 63 24.6 flash memory program/erase characteristics.. 67 25. sample characteristics............................................ 68 26. mask options ............................................................ 74 27. ordering information................................................ 75 28. package dimension. .............. .............. .............. ....... 77 29. major changes in this edition ................................ 84 document history page ................................................. 87 sales, solutions, and legal information ...................... 88 document number: 002-04629 rev. *d page 3 of 88 mb95560h series mb95570h series mb95580h series 1. product line-up ? mb95560h series part number parameter mb95f562h mb95f563h mb95f564h mb95f562k mb95f563k mb95f564k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 16 ?cmos i/o :15 ? n-ch open drain: 1 ? i/o ports (max) : 17 ? cmos i/o : 15 ? n-ch open drain: 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? both clock synchronous serial data transfer an d clock asynchronous serial data transfer are enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 6 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an "8-bit timer u 2 channels" or a "16-bit timer u 1 channel". ? it has the following functions: interval timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from intern al clocks (7 types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). document number: 002-04629 rev. *d page 4 of 88 mb95560h series mb95570h series mb95580h series ? mb95570h series part number parameter mb95f562h mb95f563h mb95f564h mb95f562k mb95f563k mb95f564k watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embe dded algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package wnp032 soj020 stg020 part number parameter mb95f572h mb95f573h mb95f574h mb95f572k mb95f573k mb95f574k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 4 ?cmos i/o :3 ? n-ch open drain: 1 ? i/o ports (max) : 5 ? cmos i/o : 3 ? n-ch open drain: 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart no lin-uart 8/10-bit a/d converter 2 channels 8-bit or 10-bit resolution can be selected. number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years document number: 002-04629 rev. *d page 5 of 88 mb95560h series mb95570h series mb95580h series ? mb95580h series 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer u 2 channels" or a "16-bit timer u 1 channel". ? it has the following functions: interval timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from intern al clocks (7 types) and external clocks. ? it can output square wave. external interrupt 2 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embe dded algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package pda008 sod008 part number parameter mb95f582h mb95f583h mb95f584h mb95f582k mb95f583k mb95f584k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 12 ?cmos i/o :11 ? n-ch open drain: 1 ? i/o ports (max) : 13 ? cmos i/o : 11 ? n-ch open drain: 2 part number parameter mb95f572h mb95f573h mb95f574h mb95f572k mb95f573k mb95f574k number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years document number: 002-04629 rev. *d page 6 of 88 mb95560h series mb95570h series mb95580h series time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? both clock synchronous serial data transfer an d clock asynchronous serial data transfer are enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 5 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer u 2 channels" or a "16-bit timer u 1 channel". ? it has the following functions: interval timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from intern al clocks (7 types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embe dded algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package wnp032 stb016 so016 part number parameter mb95f582h mb95f583h mb95f584h mb95f582k mb95f583k mb95f584k number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years document number: 002-04629 rev. *d page 7 of 88 mb95560h series mb95570h series mb95580h series 2. packages and corresponding products ? mb95560h series ? mb95570h series ? mb95580h series 2 : available x: unavailable part number package mb95f562h mb95f562k mb95f563h mb95f563k mb95f564h mb95f564k wnp032 2 2 2 2 2 2 soj020 2 2 2 2 2 2 stg020 2 2 2 2 2 2 stb016 xxxxxx so016 xxxxxx pda008 xxxxxx sod008 xxxxxx part number package mb95f572h mb95f572k mb95f573h mb95f573k mb95f574h mb95f574k wnp032 xxxxxx soj020 xxxxxx stg020 xxxxxx stb016 xxxxxx so016 xxxxxx pda008 2 2 2 2 2 2 sod008 2 2 2 2 2 2 part number package mb95f582h mb95f582k mb95f583h mb95f583k mb95f584h mb95f584k wnp032 2 2 2 2 2 2 soj020 xxxxxx stg020 xxxxxx stb016 2 2 2 2 2 2 so016 2 2 2 2 2 2 pda008 xxxxxx sod008 xxxxxx document number: 002-04629 rev. *d page 8 of 88 mb95560h series mb95570h series mb95580h series 3. differences among products an d notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash memory program/erase. for details of current consumption, see ?electrical characteristics?. ? package for details of information on each package, see ?package s and corresponding products ? and ?package dimension?. ? operating voltage the operating voltage varies, depending on whet her the on-chip debug function is used or not. for details of the operating voltage, see ?electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 21 example of serial programming conn ection? in ?new 8fx mb95560h/570h/580h hardware manual?. document number: 002-04629 rev. *d page 9 of 88 mb95560h series mb95570h series mb95580h series 4. pin assignment soj020 stg020 (mb95560h series) p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p02/int02/an02/sck p01/an01 p00/an00 p64/ec1 x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc c rst/pf2 to10/p62 to11/p63 (top view) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 nc nc nc nc nc nc p07/int07 p12/ec0/dbg x1/pf1 x0/pf0 v ss x1a/pg2 x0a/pg1 vcc (top view) wnp032 (mb95560h series) 32 31 30 29 28 27 nc 26 nc 25 24 23 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot 22 21 20 19 p02/int02/an02/sck 18 p01/an01 17 1 2 3 4 5 6 c7 rst/pf2 8 to11/p63 to10/p62 9 10 nc nc nc 11 12 13 nc 14 p00/an00 15 p64/ec1 16 the number of usable pins is 20. document number: 002-04629 rev. *d page 10 of 88 mb95560h series mb95570h series mb95580h series stb016 so016 (mb95580h series) pda008 sod008 (mb95570h series) p12/ec0/dbg p06/int06/to01 p05/an05/to00 p04/int04/an04/ec0 vss vcc c rst/pf2 (top view) 8 7 6 5 1 2 3 4 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot p01/an01 p02/int02/an02/sck x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc rst/pf2 c (top view) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 nc nc nc nc nc nc p07/int07 p12/ec0/dbg x1/pf1 x0/pf0 v ss x1a/pg2 x0a/pg1 vcc (top view) wnp032 (mb95580h series) 32 31 30 29 28 27 nc 26 nc 25 24 23 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 p03/int03/an03/sot 22 21 20 19 p02/int02/an02/sck 18 p01/an01 17 1 2 3 4 5 6 c7 rst/pf2 8 nc nc 9 10 nc nc nc 11 12 13 nc 14 nc 15 nc 16 the number of usable pins is 16. document number: 002-04629 rev. *d page 11 of 88 mb95560h series mb95570h series mb95580h series 5. pin functions (mb 95560h series, 32 pins) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 c ? decoupling capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin on mb95f562h/f563h/f564h 9 p63 e general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 10 p62 e general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 11 nc ? it is an internally connected pin. always leave it unconnected. 12 13 14 15 p00 d general-purpose i/o port high-current pin an00 a/d converter analog input pin 16 p64 e general-purpose i/o port high-current pin ec1 8/16-bit composite timer ch. 1 clock input pin 17 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 18 p02 d general-purpose i/o port high-current pin int02 external inte rrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin document number: 002-04629 rev. *d page 12 of 88 mb95560h series mb95570h series mb95580h series *: for the i/o circuit types, see ?i/o circuit type?. pin no. pin name i/o circuit type* function 19 p03 d general-purpose i/o port high-current pin int03 external inte rrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 20 p04 d general-purpose i/o port int04 external inte rrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 21 p05 d general-purpose i/o port high-current pin int05 external inte rrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 e general-purpose i/o port high-current pin int06 external inte rrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin 24 p07 e general-purpose i/o port high-current pin int07 external inte rrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 27 28 29 30 31 32 document number: 002-04629 rev. *d page 13 of 88 mb95560h series mb95570h series mb95580h series 6. pin functions (mb 95560h series, 20 pins) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 c ? decoupling capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin on mb95f562h/f563h/f564h 9 p62 e general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 10 p63 e general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 11 p64 e general-purpose i/o port high-current pin ec1 8/16-bit composite timer ch. 1 clock input pin 12 p00 d general-purpose i/o port high-current pin an00 a/d converter analog input pin 13 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 14 p02 d general-purpose i/o port high-current pin int02 external inte rrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 15 p03 d general-purpose i/o port high-current pin int03 external inte rrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin document number: 002-04629 rev. *d page 14 of 88 mb95560h series mb95570h series mb95580h series *: for the i/o circuit types, see ?i/o circuit type?. pin no. pin name i/o circuit type* function 16 p04 d general-purpose i/o port int04 external inte rrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 17 p05 d general-purpose i/o port high-current pin int05 external inte rrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 18 p06 e general-purpose i/o port high-current pin int06 external inte rrupt input pin to01 8/16-bit composite timer ch. 0 output pin 19 p07 e general-purpose i/o port high-current pin int07 external inte rrupt input pin 20 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin document number: 002-04629 rev. *d page 15 of 88 mb95560h series mb95570h series mb95580h series 7. pin functions (mb 95570h series, 8 pins) *: for the i/o circuit types, see ?i/o circuit type?. pin no. pin name i/o circuit type* function 1v ss ? power supply pin (gnd) 2v cc ? power supply pin 3 c ? decoupling capacitor connection pin 4 pf2 a general-purpose i/o port rst reset pin dedicated reset pin on mb95f572h/f573h/f574h 5 p04 d general-purpose i/o port int04 external inte rrupt input pin an04 a/d converter analog input pin ec0 8/16-bit composite timer ch. 0 clock input pin 6 p05 d general-purpose i/o port high-current pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 7 p06 e general-purpose i/o port high-current pin int06 external inte rrupt input pin to01 8/16-bit composite timer ch. 0 output pin 8 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin document number: 002-04629 rev. *d page 16 of 88 mb95560h series mb95570h series mb95580h series 8. pin functions (mb 95580h series, 32 pins) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 c ? decoupling capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin on mb95f582h/f583h/f584h 9 nc ? it is an internally connected pin. always leave it unconnected. 10 11 12 13 14 15 16 17 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 18 p02 d general-purpose i/o port high-current pin int02 external inte rrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 19 p03 d general-purpose i/o port high-current pin int03 external inte rrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin document number: 002-04629 rev. *d page 17 of 88 mb95560h series mb95570h series mb95580h series *: for the i/o circuit types, see ?i/o circuit type?. pin no. pin name i/o circuit type* function 20 p04 d general-purpose i/o port int04 external inte rrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 21 p05 d general-purpose i/o port high-current pin int05 external inte rrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 e general-purpose i/o port high-current pin int06 external inte rrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin 24 p07 e general-purpose i/o port high-current pin int07 external inte rrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 27 28 29 30 31 32 document number: 002-04629 rev. *d page 18 of 88 mb95560h series mb95570h series mb95580h series 9. pin functions (mb 95580h series, 16 pins) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 pf2 a general-purpose i/o port rst reset pin dedicated reset pin on mb95f582h/f583h/f584h 8 c ? decoupling capacitor connection pin 9 p02 d general-purpose i/o port high-current pin int02 external inte rrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 10 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 11 p03 d general-purpose i/o port high-current pin int03 external inte rrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 12 p04 d general-purpose i/o port int04 external inte rrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin document number: 002-04629 rev. *d page 19 of 88 mb95560h series mb95570h series mb95580h series *: for the i/o circuit types, see ?i/o circuit type?. pin no. pin name i/o circuit type* function 13 p05 d general-purpose i/o port high-current pin int05 external inte rrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 14 p06 e general-purpose i/o port high-current pin int06 external inte rrupt input pin to01 8/16-bit composite timer ch. 0 output pin 15 p07 e general-purpose i/o port high-current pin int07 external inte rrupt input pin 16 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin document number: 002-04629 rev. *d page 20 of 88 mb95560h series mb95570h series mb95580h series 10. i/o circuit type type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m : ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx.10 m : ? cmos output ? hysteresis input ? pull-up control available n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control document number: 002-04629 rev. *d page 21 of 88 mb95560h series mb95570h series mb95580h series 11. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failu re is greatly affected by the conditions in which they are used (circuit conditions, enviro nmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability fr om your cypress semiconductor devices. 11.1 precautions for product design this section describes precautions when designing electronic equipment usin g semiconductor devices. x absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of certain established limits, called abso lute maximum ratings. do not exceed these ratings. x recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warran ted when operated within these ranges. always use semiconductor devices wit hin the recommended operating conditio ns. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating condit ions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative before- hand. type circuit remarks d ? cmos output ? hysteresis input ? pull-up control available ? analog input e ? cmos output ? hysteresis input ? pull-up control available f ? n-ch open drain output ? hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output document number: 002-04629 rev. *d page 22 of 88 mb95560h series mb95570h series mb95580h series x processing and protection of pins these precautions must be followed when handling the pi ns which connect semiconductor devices to power supply and input/output functions. (1) preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maxi mum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present fo r extended periods of ti me can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. x latch-up semiconductor devices are cons tructed by the formation of p-type and n-ty pe areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junc tions (called thyristor struct ures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. caution: the occurrence of latch-up not only causes lo ss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power-on sequence. x observance of safety regulations and standards most countries in the world have established standards an d regulations regarding safety, protection from electromag- netic interference, etc. customers are requested to obse rve applicable regulations an d standards in the design of products. x fail-safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by in corporating safety design measures into your facility and equipment su ch as redundancy, fire protection, and prevention of over-current le vels and other abnormal operating conditions. x precautions related to usage of devices cypress semiconductor devices are intended for use in sta ndard applications (computers, office automation and other office equipment, industrial, communications, and measur ement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy co ntrols, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to co nsult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. document number: 002-04629 rev. *d page 23 of 88 mb95560h series mb95570h series mb95580h series 11.2 precautions for package mounting package mounting may be either lead insertion type or surf ace mount type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for detailed information about mount conditions, contact your sales representative. x lead insertion type mounting of lead insertion type packages onto printed ci rcuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally in volves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applyi ng liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. x surface mount type surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open conn ections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting tec hniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for ea ch product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. x lead-free packaging caution: when ball grid ar ray (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use. x storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natu ral environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and ca using packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages se miconductor devices in highly moisture -resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum lami nate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. x baking packages that have absorbed moisture may be de-moistu rized by baking (heat drying). follow the cypress recom- mended conditions for baking. condition: 125c/24 h x static electricity because semiconductor devic es are particularly susceptible to damage by static electricity, you must take the following precautions: document number: 002-04629 rev. *d page 24 of 88 mb95560h series mb95570h series mb95580h series (1) maintain relative humid ity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m : ). wearing of conductive clothing and shoes, use of conduc tive floor mats and other me asures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti-static measures. (5) avoid the use of styrofoam or ot her highly static-prone materials for storage of completed board assemblies. 11.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in de vices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. (2) discharge of static electricity when high-voltage charges exis t close to semiconductor devices, discha rges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. (3) corrosive gase s, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions th at will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are fl ammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental conditions should consult with sales repres entatives. 12. notes on device handling ? preventing latch-ups when using the device, ensure that the voltage app lied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "24.1 absolute maximum ratings" of "electrical characteristics" is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply cu rrent increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage document number: 002-04629 rev. *d page 25 of 88 mb95560h series mb95570h series mb95580h series supply voltage must be stabilized. a malfunction may occur when power supp ly voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the v cc power supply voltage. as a rule of voltage stabilizati on, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 13. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component ma y be permanently damaged due to malfunctions or latch- ups. always pull up or pull down an unused input pin through a resistor of at least 2 k : . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused outp ut pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, preven t malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addit ion, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of ap proximately 0.1 f as a decoupling capacitor between the v cc pin and the v ss pin at a location close to this device. ?dbg pin connect the dbg pin to an external pull-up resistor of 2 k : or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. si nce the actual pull-up resi stance depends on the tool used and the interconnection length, refer to the t ool document when selecting a pull-up resistor. ?rst pin connect the rst pin to an external pull-up resistor of 2 k : or above. to prevent the device from unintentionally entering the rese t mode due to noise, minimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after po wer-on. in addition, the reset output of the pf2/rst pin can be enabled by the rstoe bit in the sysc register, and the rese t input function and th e general purpose i/o function can be selected by th e rsten bit in the sysc register. ?c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, mini mize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. document number: 002-04629 rev. *d page 26 of 88 mb95560h series mb95570h series mb95580h series 14. block diagram (mb95560h series) c cs dbg rst ? dbg/rst /c pins connection diagram reset with lvd dual operation flash with security function (8/12/20 kbyte) f 2 mc-8fx cpu ram (240/496 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt lin-uart 8/16-bit composite timer ch. 0 8/10-bit a/d converter 8/16-bit composite timer ch. 1 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p02 *3 /int02 to p07 *3 /int07 (p02 *3 /sck) (p03 *3 /sot) (p04/sin) c (p12 *1 /dbg) (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) (p00 *3 /an00 to p05 *3 /an05) (p62 *3 /to10) (p63 *3 /to11) p64 *3 /ec1 vcc vss *1: *2: *3: pf2 and p12 are n-ch open drain pins. software option p00 to p03, p05 to p07 and p62 to p64 are high-current pins. internal bus note: pins in parentheses indicate that functions of those pins are shared among different resources. document number: 002-04629 rev. *d page 27 of 88 mb95560h series mb95570h series mb95580h series 15. block diagram (mb95570h series) reset with lvd dual operation flash with security function (8/12/20 kbyte) f 2 mc-8fx cpu ram (240/496 bytes) interrupt controller cr oscillator clock control on-chip debug wild register external interrupt 8/16-bit composite timer ch. 0 8/10-bit a/d converter port port pf2 *1 /rst *2 p04/int04, p06 *3 /int06 c (p12 *1 /dbg) (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) p05 *3 /an05, (p04/an04) vcc vss *1: *2: *3: pf2 and p12 are n-ch open drain pins. software option p05 and p06 are high-current pins. internal bus note: pins in parentheses indicate that functions of those pins are shared among different resources. document number: 002-04629 rev. *d page 28 of 88 mb95560h series mb95570h series mb95580h series 16. block diagram (mb95580h series) reset with lvd dual operation flash with security function (8/12/20 kbyte) f 2 mc-8fx cpu ram (240/496 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt lin-uart 8/16-bit composite timer ch. 0 8/10-bit a/d converter port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p02 *3 /int02 to p07 *3 /int07 (p02 *3 /sck) (p03 *3 /sot) (p04/sin) c (p12 *1 /dbg) (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) (p01 *3 /an01 to p05 *3 /an05) vcc vss *1: *2: *3: pf2 and p12 are n-ch open drain pins. software option p01 to p03 and p05 to p07 are high-current pins. internal bus note: pins in parentheses indicate that functions of those pins are shared among different resources. document number: 002-04629 rev. *d page 29 of 88 mb95560h series mb95570h series mb95580h series 17. cpu core ? memory space the memory space of the mb95560h/570h/ 580h is 64 kbyte in size, and consis ts of an i/o area, a data area, and a program area. the memory space includes areas intended fo r specific purposes such as general-purpose registers and a vector table. the memory maps of the mb95560h/570h/580h are shown below.8 ? memory maps i/o area access prohibited ram 496 bytes register access prohibited extension i/o area access prohibited flash 20 kbyte 0000 h 0080 h 0090 h 0100 h 0200 h 0280 h 0f80 h 1000 h b000 h ffff h mb95f564h/f564k/f574h/ f574k/f584h/f584k i/o area access prohibited ram 496 bytes register access prohibited access prohibited extension i/o area access prohibited flash 8 kbyte 0000 h 0080 h 0090 h 0100 h 0280 h 0200 h 0f80 h 1000 h b000 h c000 h e000 h ffff h mb95f563h/f563k/f573h/ f573k/f583h/f583k i/o area access prohibited ram 240 bytes register access prohibited extension i/o area access prohibited access prohibited flash 4 kbyte flash 4 kbyte flash 4 kbyte 0000 h 0080 h 0090 h 0100 h 0180 h 0f80 h 1000 h b000 h c000 h f000 h ffff h mb95f562h/f562k/f572h/ f572k/f582h/f582k document number: 002-04629 rev. *d page 30 of 88 mb95560h series mb95570h series mb95580h series 18. i/o map (mb95560h series) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting re gister r/w 11111111 b 0006 h pllc pll control register r/w 000x0000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock contro l register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0032 h ? (disabled) ? ? 0033 h pul6 port 6 pull-up register r/w 00000000 b 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 r/w 00000000 b 003a h to 0048 h ? (disabled) ? ? document number: 002-04629 rev. *d page 31 of 88 mb95560h series mb95570h series mb95580h series address register abbreviation register name r/w initial value 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage sele ction id register r/w 00000000 b 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial stat us register r/w 00001000 b 0053 h rdr lin-uart receive dat a register r/w 00000000 b tdr lin-uart transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt leve l setting register 0 r/w 11111111 b 007a h ilr1 interrupt leve l setting register 1 r/w 11111111 b 007b h ilr2 interrupt leve l setting register 2 r/w 11111111 b 007c h ilr3 interrupt leve l setting register 3 r/w 11111111 b 007d h ilr4 interrupt leve l setting register 4 r/w 11111111 b 007e h ilr5 interrupt leve l setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b document number: 002-04629 rev. *d page 32 of 88 mb95560h series mb95570h series mb95580h series address register abbreviation register name r/w initial value 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 status control register 0 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 status control register 0 r/w 00000000 b 0f99 h t11dr 8/16-bit composite timer 11 data register r/w 00000000 b 0f9a h t10dr 8/16-bit composite timer 10 data register r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 00000000 b 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (l ower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature depen dent adjustment register r/w 000xxxxx b 0fe8 h sysc system configuratio n register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r 00000000 b document number: 002-04629 rev. *d page 33 of 88 mb95560h series mb95570h series mb95580h series ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0feb h wdth watchdog timer selection id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. document number: 002-04629 rev. *d page 34 of 88 mb95560h series mb95570h series mb95580h series 19. i/o map (mb95570h series) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting re gister r/w 11111111 b 0006 h pllc pll control register r/w 000x0000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock contro l register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h , 002b h ? (disabled) ? ? 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0035 h ? (disabled) ? ? 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h to 0049 h ? (disabled) ? ? 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage sele ction id register r/w 00000000 b 004f h to 006b h ? (disabled) ? ? document number: 002-04629 rev. *d page 35 of 88 mb95560h series mb95570h series mb95580h series address register abbreviation register name r/w initial value 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt leve l setting register 0 r/w 11111111 b 007a h ilr1 interrupt leve l setting register 1 r/w 11111111 b 007b h , 007c h ? (disabled) ? ? 007d h ilr4 interrupt leve l setting register 4 r/w 11111111 b 007e h ilr5 interrupt leve l setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h to 0fc2 h ? (disabled) ? ? document number: 002-04629 rev. *d page 36 of 88 mb95560h series mb95570h series mb95580h series ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (l ower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature depen dent adjustment register r/w 000xxxxx b 0fe8 h sysc system configuratio n register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r 00000000 b 0feb h wdth watchdog timer selection id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. document number: 002-04629 rev. *d page 37 of 88 mb95560h series mb95570h series mb95580h series 20. i/o map (mb95580h series) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting re gister r/w 11111111 b 0006 h pllc pll control register r/w 000x0000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock contro l register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage sele ction id register r/w 00000000 b 004f h ? (disabled) ? ? document number: 002-04629 rev. *d page 38 of 88 mb95560h series mb95570h series mb95580h series address register abbreviation register name r/w initial value 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial stat us register r/w 00001000 b 0053 h rdr lin-uart receive dat a register r/w 00000000 b tdr lin-uart transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt leve l setting register 0 r/w 11111111 b 007a h ilr1 interrupt leve l setting register 1 r/w 11111111 b 007b h ilr2 interrupt leve l setting register 2 r/w 11111111 b 007c h ? (disabled) ? ? 007d h ilr4 interrupt leve l setting register 4 r/w 11111111 b 007e h ilr5 interrupt leve l setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b document number: 002-04629 rev. *d page 39 of 88 mb95560h series mb95570h series mb95580h series ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (l ower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature depen dent adjustment register r/w 000xxxxx b 0fe8 h sysc system configuratio n register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r 00000000 b 0feb h wdth watchdog timer selection id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. document number: 002-04629 rev. *d page 40 of 88 mb95560h series mb95570h series mb95580h series 21. interrupt source table (mb95560h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] document number: 002-04629 rev. *d page 41 of 88 mb95560h series mb95570h series mb95580h series 22. interrupt source table (mb95570h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low ? irq01 fff8 h fff9 h l01 [1:0] ? irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 ? irq03 fff4 h fff5 h l03 [1:0] ? ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] ? irq07 ffec h ffed h l07 [1:0] ?irq08ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] document number: 002-04629 rev. *d page 42 of 88 mb95560h series mb95570h series mb95580h series 23. interrupt source table (mb95580h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ?irq09ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] document number: 002-04629 rev. *d page 43 of 88 mb95560h series mb95570h series mb95580h series 24. electrical characteristics 24.1 absolute maximum ratings *1: these parameters are based on the condition that v ss is 0.0 v. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss 0.3 v ss 6v input voltage* 1 v i v ss 0.3 v ss 6v*2 output voltage* 1 v o v ss 0.3 v ss 6v*2 maximum clamp current i clamp 2 2 ma applicable to specific pins *3 total maximum clamp current 6 |i clamp | ? 20 ma applicable to specific pins *3 ?l? level maximum output current i ol ?15ma ?l? level average current i olav1 ? 4 ma other than p00 to p03, p05 to p07, p62 to p64 *4 average output current= operating current u operating ratio (1 pin) i olav2 12 p00 to p03, p05 to p07, p62 to p64 *4 average output current= operating current u operating ratio (1 pin) ?l? level total maximum output current 6 i ol ? 100 ma ?l? level total average output current 6 i olav ?50ma total average output current= operating current u operating ratio (total number of pins) ?h? level maximum output current i oh ? 15 ma ?h? level average current i ohav1 ? 4 ma other than p00 to p03, p05 to p07, p62 to p64 *4 average output current= operating current u operating ratio (1 pin) i ohav2 8 p00 to p03, p05 to p07, p62 to p64 *4 average output current= operating current u operating ratio (1 pin) ?h? level total maximum output current 6 i oh ? 100 ma ?h? level total average output current 6 i ohav ? 50 ma total average output current= operating current u operating ratio (total number of pins) power consumption p d ? 320 mw operating temperature t a 40 85 c storage temperature t stg 55 150 c document number: 002-04629 rev. *d page 44 of 88 mb95560h series mb95570h series mb95580h series *2: v i and v o must not exceed v cc 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/ from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: applicable to the following pins: p00 to p07, p62 to p64, pf0, pf1, pg1, pg2 (p00, and p62 to p64 are only available on mb95f562h/f562k/f563h/f563k/f564h/f564k. p01, p02, p03, p07, pf0. pf1, pg1, and pg2 are only avail- able on mb95f562h/f562k/f563h/f563k/f564h /f564k/f582h/f582k/f583h/f583k/f584h/f584k.) ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontro ller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is in put is below the standard value, irrespecti ve of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcon troller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, si nce power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: *4: p62 and p63 are only available on mb 95f562h/f562k/f563h/f563k/f564h/f564k. warning: semiconductor devices may be permanently da maged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolu te maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit document number: 002-04629 rev. *d page 45 of 88 mb95560h series mb95570h series mb95580h series 24.2 recommended operating conditions (v ss = 0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: the minimum power supply voltage becomes 2.88 v when a product with the low-voltage detection reset is used. *3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be und er their recommended op erating condition. operation under any conditio ns other than these conditions may adve rsely affect reliab ility of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1, * 2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode decoupling capacitor c s 0.022 1 f *3 operating temperature t a 40 85 c other than on-chip debug mode 5 35 on-chip debug mode c cs dbg * rst ? dbg / rst / c pins connection diagram *: connect the dbg pin to an exte rnal pull-up resistor of 2 k : or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the rese t output is released. the dbg pin becomes a com- munication pin in debug mode. since the actual pull- up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. document number: 002-04629 rev. *d page 46 of 88 mb95560h series mb95570h series mb95580h series 24.3 dc characteristics (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) parameter symbol pin name condition value unit remarks min typ max "h" level input voltage v ih p04 ? 0.7 v cc ?v cc 0.3 v hysteresis input v ihs p00* 3 to p03* 4 , p05 to p07* 4 , p12, p62 to p64* 3 , pf0* 4 , pf1* 4 , pg1* 4 , pg2* 4 ? 0.8 v cc ?v cc 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ?v cc 0.3 v hysteresis input ?l? level input voltage v il p04 ? v ss 0.3 ? 0.3 v cc v hysteresis input v ils p00* 3 to p03* 4 , p05 to p07* 4 , p12, p62 to p64* 3 , pf0* 4 , pf1* 4 , pg1* 4 , pg2* 4 ?v ss 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, pf2 ? v ss 0.3 ? v ss 5.5 v ?h? level output voltage v oh1 p04, pf0* 4 , pf1* 4 , pg1* 4 , pg2 i oh = 4 ma v cc 0.5 ? ? v v oh2 p00* 3 to p03* 4 , p05 to p07* 4 , p62 to p64* 3 i oh = 8 ma v cc 0.5 ? ? v ?l? level output voltage v ol1 p04, p12, pf0 to pf2* 4 , pg1* 4 , pg2* 4 i ol = 4 ma ? ? 0.4 v v ol2 p00* 3 to p03* 4 , p05 to p07* 4 , p62 to p64* 3 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc 5? 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull p00* 3 to p07* 4 , p62 to p64* 3 , pg1* 4 , pg2* 4 v i = 0 v 25 50 100 k : when the internal pull-up resistor is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf document number: 002-04629 rev. *d page 47 of 88 mb95560h series mb95570h series mb95580h series (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) parameter symbol pin name condition value unit remarks min typ * 1 max * 2 power supply current* 5 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?3.54.4ma except during flash memory programming and erasing ?7.49.8ma during flash memory programming and erasing ? 5.1 6.4 ma at a/d conversion i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?1.21.5ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = 25 c ?6571a i ccls * 6 f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = 25 c ?5.4 7 a in deep standby mode i cct * 6 f cl = 32 khz watch mode t a = 25 c ?4.86.9a in deep standby mode i ccmcr v cc f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.11.4ma i ccscr sub-cr clock mode (divided by 2) t a = 25 c ?5864a i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = 25 c ? 290 340 a in deep standby mode i cch main stop mode (single external clock product)/ substop mode (dual external clock product) t a = 25 c ?4.16.5a in deep standby mode document number: 002-04629 rev. *d page 48 of 88 mb95560h series mb95570h series mb95580h series (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: v cc = 5.0 v, t a = 25 c *2: v cc = 5.5 v, t a = 85 c (unless otherwise specified) *3: p00, p62, p63 and p64 are only availabl e on mb95f562h/f562k/f563h/f563k/f564h/f564k. *4: p01, p02, p03, p07, pf0, pf1, pg1 and pg2 are on ly available on mb95f562h/f562k/f563h/f563k/f564h/f564k/ f582h/f582k/f583h/f583k/f584h/f584k. *5: ? the power supply current is determined by the external clock. when the low-voltage detection option is selected, the power-supply current will be the sum of adding the curr ent consumption of the low- voltage detection circuit (i lvd ) to one of the value from i cc to i cch . in addition, when both th e low-voltage detection op tion and the cr oscillator are selected, the power supp ly current will be the sum of adding up th e current consumption of the low-voltage detection circuit, the current cons umption of the cr oscillators (i crh , i crl ) and a specified value. in on-chip debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. ? see ?24.4 ac characteristics: clock timing? for f ch and f cl . ? see ?24.4 ac characteristics: so urce clock / machine clock? for f mp and f mpl . *6: in sub-cr clock mode, the power supply current value is the sum of adding i crl to i ccls or i cct . in addition, when the sub-cr clock mode is selected with f mpl being 50 khz, the current consumption increases accordingly. parameter symbol pin name condition value unit remarks min typ * 1 max * 2 power supply current* 5 i lvd v cc current consumption for the low-voltage detection circuit ?3.66.6a i crh current consumption for the main cr oscillator ? 220 280 a i crl current consumption for the sub-cr oscillator oscillating at 100 khz ?5.19.3a i nstby current consumption difference between normal standby mode and deep standby mode t a = 25 c ?2030a document number: 002-04629 rev. *d page 49 of 88 mb95560h series mb95570h series mb95580h series 24.4 ac characteristics 24.4.1 clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = 40 c to 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 c d t a d 70 c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? 40 c d t a < 0 c, 70 c < t a d 85 c f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 c d t a d 70 c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? 40 c d t a < 0 c, 70 c < t a d 85 c 9.8 10 10.2 mhz operating conditions ? pll multiplication rate: 2.5 ?0 c d t a d 70 c 9.5 10 10.5 mhz operating conditions ? pll multiplication rate: 2.5 ? 40 c d t a < 0 c, 70 c < t a d 85 c 11.761212.24mhz operating conditions ? pll multiplication rate: 3 ?0 c d t a d 70 c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? 40 c d t a < 0 c, 70 c < t a d 85 c 15.681616.32mhz operating conditions ? pll multiplication rate: 4 ?0 c d t a d 70 c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? 40 c d t a < 0 c, 70 c < t a d 85 c f cl x0a, x1a ? ? 32.768 ? khz when the suboscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used document number: 002-04629 rev. *d page 50 of 88 mb95560h series mb95570h series mb95580h series (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = 40 c to 85 c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when an external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 x1: open 33.4 ? ? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 12.4 ? ? ns t wh2 , t wl2 x0a ? ? 15.2 ? s input clock rising time and falling time t cr , t cf x0, x0a x1: open ? ? 5 ns when an external clock is used x0, x1, x0a, x1a *??5ns cr oscillation start time t crhwk ????50s when the main cr clock is used t crlwk ????30s when the sub-cr clock is used x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when an external clock is used x0 x1 x0 x1 f ch f ch when an external clock is used (x1 is open) x0 x1 open f ch ? figure of main clock inpu t port external connection document number: 002-04629 rev. *d page 51 of 88 mb95560h series mb95570h series mb95580h series x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external clock is used x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection document number: 002-04629 rev. *d page 52 of 88 mb95560h series mb95570h series mb95580h series 24.4.2 source cl ock / machine clock (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: this is the clock before it is divided according to the di vision ratio set by the machine cl ock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (sycc div[1:0]). in addition, a source cloc k can be selected from the following. ? main clock divided by 2 ? main cr clock ? pll multiplication of main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontrolle r. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 62.5 ? 1000 ns when the main cr clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, divided by 4 ?61?s when the suboscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 ? mhz when the main cr clock is used f spl ? 16.384 ? khz when the suboscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 1000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 4 61 ? 976.5 s when the suboscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 16 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the su boscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz document number: 002-04629 rev. *d page 53 of 88 mb95560h series mb95570h series mb95580h series f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f mcrpll (main cr pll clock) f crh (main cr clock) f cl (suboscillation clock) f crl (sub-cr clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 ? schematic diagram of th e clock generation block document number: 002-04629 rev. *d page 54 of 88 mb95560h series mb95570h series mb95580h series operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.7 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 khz 3 mhz 12.5 mhz 16.25 mhz source clock frequency (f sp ) ? operating voltage - operating frequency (t a = 40c to 85c) without the on-chip debug function ? operating voltage - operating frequency (t a = 40 c to 85 c) with the on-chip debug function document number: 002-04629 rev. *d page 55 of 88 mb95560h series mb95570h series mb95580h series 24.4.3 external reset (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: see ?source clock / machine clock? for t mclk . parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation 0.2 v cc rst 0.2 v cc t rstl document number: 002-04629 rev. *d page 56 of 88 mb95560h series mb95570h series mb95580h series 24.4.4 power-on reset (v ss = 0.0 v, t a = 40 c to 85 c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. 24.4.5 peripheral input timing (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: int04, int06 and ec0 are available on all products. *2: int02, int03, int05 and int07 are only availabl e on mb95f562h/f562k/f563h/f563k/f564h/f564k/f582h/ f582k/f583h/f583k/f584h/f584k. *3: ec1 is only available on mb95f562h/f562k/f563h/f563k/f564h/f564k. *4: see ?source clock / machine clock? for t mclk . parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07* 1, * 2 , ec0* 1 , ec1* 3 2 t mclk * 4 ?ns peripheral input ?l? pulse width t ihil 2 t mclk * 4 ?ns 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms. int02 to int07, ec0, ec1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil document number: 002-04629 rev. *d page 57 of 88 mb95560h series mb95570h series mb95580h series 24.4.6 lin-uart timing (only available on mb95f562h /f562k/f563h/f563k/f564h/f564k/f582h/f582k/f583h/f583k/f584h/ f584k) sampling is executed at the rising edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register: sces bit = 0, eccr register: scde bit = 0) (v cc = 5.0 v r 10%, av ss = v ss = 0.0 v, t a = 40 c to 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf 1 ttl 5 t mclk * 3 ?ns sck p o sot delay time t slovi sck, sot 50 50 ns valid sin o sck n t ivshi sck, sin t mclk * 3 80 ? ns sck n o valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf 1 ttl 3 t mclk * 3 t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 10 ? ns sck p o sot delay time t slove sck, sot ? 2 t mclk * 3 60 ns valid sin o sck n t ivshe sck, sin 30 ? ns sck n o valid sin hold time t shixe sck, sin t mclk * 3 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns 0.2 v cc 0.2 v cc 0.8 v cc t slovi t ivshi t shixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode document number: 002-04629 rev. *d page 58 of 88 mb95560h series mb95570h series mb95580h series sampling is executed at the fa lling edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register: sces bit = 1, eccr register: scde bit = 0) (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf 1 ttl 5 t mclk * 3 ?ns sck n o sot delay time t shovi sck, sot 50 50 ns valid sin o sck p t ivsli sck, sin t mclk * 3 80 ? ns sck p o valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf 1 ttl 3 t mclk * 3 t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 10 ? ns sck n o sot delay time t shove sck, sot ? 2 t mclk * 3 60 ns valid sin o sck p t ivsle sck, sin 30 ? ns sck p o valid sin hold time t slixe sck, sin t mclk * 3 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t slsh t shsl t r 0.8 v cc t f ? external shift clock mode document number: 002-04629 rev. *d page 59 of 88 mb95560h series mb95570h series mb95580h series 0.2 v cc 0.8 v cc 0.8 v cc t shovi t ivsli t slixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t shsl t slsh t f 0.8 v cc t r ? external shift clock mode document number: 002-04629 rev. *d page 60 of 88 mb95560h series mb95570h series mb95580h series sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is enabled * 2 . (escr register: sces bit = 0, eccr register: scde bit = 1) (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: see ?source clock / machine clock? for t mclk . sampling is executed at the fa lling edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register: sces bit = 1, eccr register: scde bit = 1) (v cc = 5.0 v r 10%, v ss = 0.0 v, t a = 40 c to 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: see ?source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf 1 ttl 5 t mclk * 3 ?ns sck n o sot delay time t shovi sck, sot 50 50 ns valid sin o sck p t ivsli sck, sin t mclk * 3 80 ? ns sck p o valid sin hold time t slixi sck, sin 0 ? ns sot o sck p delay time t sovli sck, sot 3 t mclk * 3 70 ? ns parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operating output pin: c l = 80 pf 1 ttl 5 t mclk * 3 ?ns sck p o sot delay time t slovi sck, sot 50 50 ns valid sin o sck n t ivshi sck, sin t mclk * 3 80 ? ns sck n o valid sin hold time t shixi sck, sin 0 ? ns sot o sck n delay time t sovhi sck, sot 3 t mclk * 3 70 ? ns 0.8 v cc 0.2 v cc 0.2 v cc t shovi t sovli t ivsli t slixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc document number: 002-04629 rev. *d page 61 of 88 mb95560h series mb95570h series mb95580h series 24.4.7 low-voltage detection (v ss = 0.0 v, t a = 40 c to 85 c) *: the release voltage and the detection voltage can be sele cted by using the lvd reset voltage selection id register (lvdr) in the low-voltage detection reset circuit. for details of the lvdr register, refer to ?chapter 18 low- voltage detection reset circuit? in ?new 8fx mb95560h/570h/580h hardware manual?. parameter symbol value unit remarks min typ max release voltage* v dl 2.52 2.7 2.88 v at power supply rise 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 detection voltage* v dl 2.43 2.6 2.77 v at power supply fall 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 hysteresis width v hys ? 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 650 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??30s reset detection delay time t d2 ??30s lvd threshold voltage transition stabilization time t stb 10 ? ? s 0.2 v cc 0.8 v cc 0.8 v cc t slovi t sovhi t ivshi t shixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc document number: 002-04629 rev. *d page 62 of 88 mb95560h series mb95570h series mb95580h series v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time internal reset signal document number: 002-04629 rev. *d page 63 of 88 mb95560h series mb95570h series mb95580h series 24.5 a/d converter 24.5.1 a/d converter electrical characteristics (v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = 40 c to 85 c) parameter symbol value unit remarks min typ max resolution ? ? ? 10 bit total error 3? 3lsb linearity error 2.5 ? 2.5 lsb differential linearity error 1.9 ? 1.9 lsb zero transition voltage v 0t v ss 1.5 lsb v ss 0.5 lsb v ss 2.5 lsb v full-scale transition voltage v fst v cc 4.5 lsb v cc 2 lsb v cc 0.5 lsb v compare time ? 1 ? 10 s 4.5 v d v cc d 5.5 v 3 ? 10 s 2.7 v d v cc < 4.5 v sampling time ? 0.6 ? f s 2.7 v d v cc d 5.5 v, with external impedance < 3.3 k : analog input current i ain 0.3 ? 0.3 a analog input voltage v ain v ss ?v cc v document number: 002-04629 rev. *d page 64 of 88 mb95560h series mb95570h series mb95580h series 24.5.2 notes on using a/d converter ? external impedance of analog input and its sampling time the a/d converter of the mb95 560h/570h/580h has a sample and hold circui t. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affe cting a/d conversion precision. therefore, to satisfy the a/d conver sion precision stan- dard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the exte rnal impedance so that the sampling time is longer than the minimum value. in addition, if suff icient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. ? a/d conversion error as |v cc v ss | decreases, the a/d conversion error increases proportionately. note: the values are reference values. 4.5 v v cc 5.5 v 2.7 v v cc < 4.5 v 1.45 k (max) 2.7 k (max) 14.89 pf (max) v cc r c 14.89 pf (max) comparator analog input during sampling: on r c ? analog input equivalent circuit [external impedance = 0 k to 100 k ] external impedance [k ] minimum sampling time [ s] minimum sampling time with v cc > 2.7 v minimum sampling time with v cc > 2.4 v 024681012 100000 80000 60000 40000 20000 0 [external impedance = 0 k to 20 k ] external impedance [k ] minimum sampling time [ s] 0 0.5 1 1.5 2 2.5 20000 15000 10000 5000 0 ? relationship between external impedance and minimum sampling time document number: 002-04629 rev. *d page 65 of 88 mb95560h series mb95570h series mb95580h series 24.5.3 definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?0000000000? m o ?0000000001?) of a device to the full-scale transition point (?1111111111? m o ?1111111110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a th eoretical value. the error ca n be caused by a zero tran- sition error, a full-scale transition errors, a linearity error, a quantum error, or noise. v fst ideal i/o characteristics 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from (n ? 1) h to n h {1 lsb (n-1) + 0.5 lsb} v nt total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] = v cc ? v ss 1024 (v) 1 lsb = v ss v cc v ss v cc document number: 002-04629 rev. *d page 66 of 88 mb95560h series mb95570h series mb95580h series zero transition error linearity error full-scale transition error 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output differential linearity error of digital output n v (n+1)t ? v nt 1 lsb ? 1 = linearity error of digital output n v nt ? {1 lsb n + v 0t } 1 lsb = digital output analog input 001 h 002 h 3fc h 3fd h 003 h 3fe h 3ff h 004 h actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error (n ? 2) h (n ? 1) h n h (n+1) h digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n+1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from (n ? 1) h to n h v 0t (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 2 lsb [v] ideal characteristic document number: 002-04629 rev. *d page 67 of 88 mb95560h series mb95570h series mb95580h series 24.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = 25 c, 0 cycle *2: v cc = 2.4 v, t a = 85 c, 100000 cycles *3: this value was converted from the resu lt of a technology reliability assessmen t. (the value was converted from the result of a high temperature accelerated test using the arrhenius equation with an average temperature of 85 c). parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing 00 h prior to erasure is excluded. sector erase time (16 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing 00 h prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 2.4 ? 5.5 v flash memory data retention time 5* 3 ? ? year average t a = 85 c document number: 002-04629 rev. *d page 68 of 88 mb95560h series mb95570h series mb95580h series 25. sample characteristics ? power supply current temperature characteristics 0 5 10 15 20 234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc v cc t a 25 c, f mp 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i cc [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz 0 2 4 6 8 10 234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 2 4 6 8 10 ? 50 0 + 50 + 100 + 150 i ccs [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz 0 20 40 60 80 100 234567 i ccl [ a] v cc [v] 0 25 50 75 100 ? 50 0 + 50 + 100 + 150 i ccl [ a] t a [ c] i cc t a v cc 5.5 v, f mp 10, 16 mhz (divided by 2) main clock mode with the ex ternal clock operating i ccs v cc t a 25 c, f mp 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs t a v cc 5.5 v, f mp 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl v cc t a 25 c, f mpl 16 khz (divided by 2) subclock mode with the external clock operating i ccl t a v cc 5.5 v, f mpl 16 khz (divided by 2) subclock mode with the external clock operating document number: 002-04629 rev. *d page 69 of 88 mb95560h series mb95570h series mb95580h series 0 4 8 12 16 20 ? 50 0 + 50 + 100 + 150 i cct [ a] t a [ c] i cct t a v cc 5.5 v, f mpl 16 khz (divided by 2) watch mode with the external clock operating 0 20 10 40 30 50 70 80 60 ? 50 0 + 50 + 100 + 150 i ccls [ a] t a [ c] i ccls t a v cc 5.5 v, f mpl 16 khz (divided by 2) subsleep mode with the external clock operating 0 40 30 20 10 50 60 70 80 234567 i ccls [ a] v cc [v] 0 4 8 12 16 20 234567 i cct [ a] v cc [v] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 234567 i ccts [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 0.4 0.2 0.6 0.8 1.0 1.4 1.2 ? 50 0 + 50 + 100 + 150 i ccts [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz i ccls v cc t a 25 c, f mpl 16 khz (divided by 2) subsleep mode with the external clock operating i cct v cc t a 25 c, f mpl 16 khz (divided by 2) watch mode with the external clock operating i ccts v cc t a 25 c, f mp 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts t a v cc 5.5 v, f mp 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating document number: 002-04629 rev. *d page 70 of 88 mb95560h series mb95570h series mb95580h series 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i cch [ a] t a [ c] i cch t a v cc 5.5 v, f mpl (stop) substop mode with the external clock stopping 0 5 10 15 20 1234567 i cch [ a] v cc [v] 0 5 10 15 20 234567 i ccmcr [ma] v cc [v] 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i ccmcr [ma] t a [ c] 0 50 100 150 200 234567 i ccscr [ a] v cc [v] 0 50 100 150 200 ? 50 0 + 50 + 100 + 150 i ccscr [ a] t a [ c] i cch v cc t a 25 c, f mpl (stop) substop mode with the external clock stopping i ccmcr v cc t a 25 c, f mp 4 mhz (no division) main clock mode with the main cr clock operating i ccmcr t a v cc 5.5 v, f mp 4 mhz (no division) main clock mode with the main cr clock operating i ccscr v cc t a 25 c, f mpl 50 khz (divided by 2) subclock mode with the sub-cr clock operating i ccscr t a v cc 5.5 v, f mpl 50 khz (divided by 2) subclock mode with th e sub-cr clock operating document number: 002-04629 rev. *d page 71 of 88 mb95560h series mb95570h series mb95580h series ? input voltage characteristics 0 1 2 4 5 234567 v ihi /v ili [v] v cc [v] 3 v ihi v ili 0 1 2 4 5 234567 v ihs /v ils [v] v cc [v] 3 v ihs v ils v ihi v cc and v ili v cc t a 25 c v ihs v cc and v ils v cc t a 25 c 0 1 2 4 5 234567 v ihm /v ilm [v] v cc [v] 3 v ihm v ilm v ihm v cc and v ilm v cc t a 25 c document number: 002-04629 rev. *d page 72 of 88 mb95560h series mb95570h series mb95580h series ? output voltage characteristics 0.0 0.2 0.4 0.8 1.0 0 ? 2 ? 4 ? 6 ? 8 ? 10 v cc ? v oh2 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc v oh2 ) i oh t a 25 c v ol1 i ol t a 25 c 0.0 0.2 0.4 0.8 1.0 0 ? 2 ? 4 ? 6 ? 8 ? 10 v cc ? v oh1 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc v oh1 ) i oh t a 25 c 0.0 0.2 0.4 0246810 v ol2 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol2 i ol t a 25 c 0.0 0.2 0.4 0.8 1.0 0246810 v ol1 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v document number: 002-04629 rev. *d page 73 of 88 mb95560h series mb95570h series mb95580h series ? pull-up characteristics 0 50 100 150 200 250 23456 r pull [k ] v cc [v] r pull v cc t a 25 c document number: 002-04629 rev. *d page 74 of 88 mb95560h series mb95570h series mb95580h series 26. mask options no. part number mb95f562h mb95f563h mb95f564h mb95f572h mb95f573h mb95f574h mb95f582h mb95f583h mb95f584h mb95f562k mb95f563k mb95f564k mb95f572k mb95f573k mb95f574k mb95f582k mb95f583k mb95f584k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input document number: 002-04629 rev. *d page 75 of 88 mb95560h series mb95570h series mb95580h series 27. ordering information part number package packing mb95f562hwqn-g-sne1 mb95f562kwqn-g-sne1 mb95f563hwqn-g-sne1 mb95f563kwqn-g-sne1 mb95f564hwqn-g-sne1 mb95f564kwqn-g-sne1 32-pin plastic qfn (wnp032) tray mb95f562hwqn-g-snere1 mb95f562kwqn-g-snere1 mb95f563hwqn-g-snere1 mb95f563kwqn-g-snere1 mb95f564hwqn-g-snere1 mb95f564kwqn-g-snere1 reel mb95f562hpf-g-sne2 mb95f562kpf-g-sne2 mb95f563hpf-g-sne2 mb95f563kpf-g-sne2 MB95F564HPF-G-SNE2 mb95f564kpf-g-une2 20-pin plastic sop (soj020) tube mb95f562hpft-g-sne2 mb95f562kpft-g-sne2 mb95f563hpft-g-sne2 mb95f563kpft-g-sne2 mb95f564hpft-g-sne2 mb95f564kpft-g-une2 20-pin plastic tssop (stg020) tube mb95f562kpft-g-unere2 mb95f563hpft-g-unere2 mb95f563kpft-g-unere2 mb95f564kpft-g-unere2 reel mb95f582hwqn-g-sne1 mb95f582kwqn-g-sne1 mb95f583hwqn-g-sne1 mb95f583kwqn-g-sne1 mb95f584hwqn-g-sne1 mb95f584kwqn-g-sne1 32-pin plastic qfn (wnp032) tray mb95f582hwqn-g-snere1 mb95f582kwqn-g-snere1 mb95f583hwqn-g-snere1 mb95f583kwqn-g-snere1 mb95f584hwqn-g-snere1 mb95f584kwqn-g-snere1 reel mb95f582hpft-g-sne2 mb95f582kpft-g-sne2 mb95f583hpft-g-sne2 mb95f583kpft-g-sne2 mb95f584hpft-g-sne2 mb95f584kpft-g-sne2 16-pin plastic tssop (stb016) tube document number: 002-04629 rev. *d page 76 of 88 mb95560h series mb95570h series mb95580h series part number package packing mb95f582hpf-g-sne2 mb95f582kpf-g-sne2 mb95f583hpf-g-sne2 mb95f583kpf-g-sne2 mb95f584hpf-g-sne2 mb95f584kpf-g-sne2 16-pin plastic sop (so016) tube mb95f572hph-g-sne2 mb95f572kph-g-sne2 mb95f573hph-g-sne2 mb95f573kph-g-sne2 mb95f574hph-g-sne2 mb95f574kph-g-sne2 8-pin plastic dip (pda008) tube mb95f572hpf-g-sne2 mb95f572kpf-g-sne2 mb95f573hpf-g-sne2 mb95f573kpf-g-sne2 mb95f574hpf-g-sne2 mb95f574kpf-g-sne2 8-pin plastic sop (sod008) tube document number: 002-04629 rev. *d page 77 of 88 mb95560h series mb95570h series mb95580h series 28. package dimension package type package code qfn 32 wnp032 002-15160 ** document number: 002-04629 rev. *d page 78 of 88 mb95560h series mb95570h series mb95580h series package type package code sop 20 soj020 002-16348 ** document number: 002-04629 rev. *d page 79 of 88 mb95560h series mb95570h series mb95580h series package type package code tssop 20 stg020 002-15916 ** document number: 002-04629 rev. *d page 80 of 88 mb95560h series mb95570h series mb95580h series package type package code tssop 16 stb016 002-15914 ** document number: 002-04629 rev. *d page 81 of 88 mb95560h series mb95570h series mb95580h series package type package code sop 16 so016 002-15861 ** document number: 002-04629 rev. *d page 82 of 88 mb95560h series mb95570h series mb95580h series package type package code dip 8 pda008 002-16909 ** document number: 002-04629 rev. *d page 83 of 88 mb95560h series mb95570h series mb95580h series package type package code sop 8 sod008 002-15858 ** document number: 002-04629 rev. *d page 84 of 88 mb95560h series mb95570h series mb95580h series 29. major changes in this edition spansion publication number: ds702-00010 page section details ?? changed the series name. mb95560h series o mb95560h/570h/580h series added information on the mb95570h series. added information on the mb95580h series. 27 document number: 002-04629 rev. *d page 85 of 88 mb95560h series mb95570h series mb95580h series 48 2. recommended operating conditions revised note *2. the value is 2.88 v when the low-voltage detection reset is used. o the minimum power supply voltage becomes 2.18 v when a product with the low- voltage detection reset is used. corrected the following statement in note *3. the decoupling capacitor for the v cc pin must have a capacitance larger than c s . o the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . revised the remark in ?? dbg/rst /c pins connection diagram?. 49 3. dc characteristics revised the remark of the parameter ?input leak current (hi-z output leak current)?. when pull-up resistance is disabled o when the internal pull-up resistor is disabled renamed the parameter ?pull-up resistance? to ?internal pull-up resistor?. revised the remark of the parameter ?internal pull-up resistor?. when pull-up resistance is enabled o when the internal pull-up resistor is enabled 53 4. ac characteristics (1) clock timing corrected the pin names of the parameter ?input clock rising time and falling time?. x0 o x0, x0a x0, x1 o x0, x1, x0a, x1a page section details document number: 002-04629 rev. *d page 86 of 88 mb95560h series mb95570h series mb95580h series ? major changes from third edition to fourth edition note: please see ?document history ? about later revised information. page section details 23 to 26 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? document number: 002-04629 rev. *d page 87 of 88 mb95560h series mb95570h series mb95580h series document history page document title: mb95560h series, mb95570h series, mb95580h series, new 8fx 8-bit microcontrollers document number: 002-04629 revision ecn orig. of change submission date description of change ** - akih 05/27/2013 migrated to cypress and assigned document number 002-04629. no change to document contents or format. *a 5193921 akih 03/29/2016 updated to cypress template updated 24.4.3 external reset added mb95f564kpf-g-une2, mb95f564kpft-g-une2 in "ordering information". *b 5420206 hter 02/06/2017 changed package code as the follow ing in 1.product line-up (page4, 6), 2.packages and corresponding products (page 7), 4.pin assignment (page 9 to 10), 27.ordering information (page 75 to 76) and 28.package dimensions (page 77 to 83). ?lcc-32p-m19? to ?wnp032? ?fpt-20p-m09? to ?soj020? ?fpt-20p-m10? to ?stg020? ?fpt-16p-m08? to ?stb016? ?fpt-16p-m23? to ?so016? ?dip-8p-m03? to ?pda008? ?fpt-8p-m08? to ?sod008? added part number ?mb95f564kpft-g-unere2, mb95f562kpft-g-unere2, mb95f563kpft-g-unere2? in 27.ordering information (page 75). deleted part number ?mb95f564kpf-g-sne2, mb95f564kpft-g-sne2? in 27.ordering infor- mation (page 75) . *c 5761469 aesatp12 06/08/2017 updated logo and copyright. *d hual 09/27/2017 added part number ?mb95f563hpft-g-unere2? and packing information in 27.ordering information (page 75). 5895915 document number: 002-04629 rev. *d revised september 27, 2017 page 88 of 88 ? cypress semiconductor corporation, 201 1 -2017. this do cument is the property of cypress semiconduc tor cor poration and its subsidiaries, including s p ansion llc ("cypress"). this document, inc luding any software or firmware included or referenced in this document ("software" ) , is owned by cypress under the intellec tual property laws and treatie s of the united states and other c ountries worldwide. cy press reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, tr adem arks, or other intellectual property rights. if the softwar e is n ot accompanied by a license agreement and you do not otherwise have a writte n agreement with cypres s governing the use of the software, then cypress hereby grants you a personal, non-ex c lusive, nontransfe rable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to m odify and reproduce the software solely for use with cypress hard ware products, only intern ally within your organization, and ( b) to distribute the software in binary code form externally to end user s ( either directly or indirectly through r esellers and distributors), solely for use on cypress hardware product units, an d (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypr ess, unmodified) to make, use, distribute, and import the software solely for use with cy pres s hardware pr oduct s. any other use, reproduction, m odification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, 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life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion 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